ATA8741-PXQW【PDF 171/238 页】MCU W/TRANSMITTER ASK/FSK 24QFN

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Sheet目录52

167页 168页 169页 170页 [171页]172页 173页 174页 175页

171

9140CINDCO02/10

ATA8741

25.10.4 ADCSRB ADC Control and Status Register B

" Bits 7 BIN: Bipolar Input Mode

The gain stage is working in the unipolar mode as default, but the bipolar mode can be selected

by writing the BIN bit in the ADCSRB register. In the unipolar mode only one-sided conversions

are supported and the voltage on the positive input must always be larger than the voltage on

the negative input. Otherwise the result is saturated to the voltage reference. In the bipolar mode

two-sided conversions are supported and the result is represented in the twos complement

form. In the unipolar mode the resolution is 10 bits and the bipolar mode the resolution is 9 bits +

1 sign bit.

" Bit 6 ACME: Analog Comparator Multiplexer Enable

See ADCSRB ADC Control and Status Register B on page 152.

" Bit 5 Res: Reserved Bit

This bit is reserved bit in the ATtiny24/44/84 and will always read as what was wrote there.

" Bit 4 ADLAR: ADC Left Adjust Result

The ADLAR bit affects the presentation of the ADC conversion result in the ADC Data Register.

Write one to ADLAR to left adjust the result. Otherwise, the result is right adjusted. Changing the

ADLAR bit will affect the ADC Data Register immediately, regardless of any ongoing conver-

sions. For a comple the description of this bit, see ADCL and ADCH ADC Data Register on

page 170.

" Bit 3 Res: Reserved Bit

This bit is reserved bit in the ATtiny24/44/84 and will always read as what was wrote there.

" Bits 2:0 ADTS2:0: ADC Auto Trigger Source

If ADATE in ADCSRA is written to one, the value of these bits selects which source will trigger

an ADC conversion. If ADATE is cleared, the ADTS2:0 settings will have no effect. A conversion

will be triggered by the rising edge of the selected Interrupt Flag. Note that switching from a trig-

ger source that is cleared to a trigger source that is set, will generate a positive edge on the

trigger signal. If ADEN in ADCSRA is set, this will start a conversion. Switching to Free Running

mode (ADTS[2:0]=0) will not cause a trigger event, even if the ADC Interrupt Flag is set.

Bit

0x03 (0x23)

BIN

ACME

ADLAR

ADTS2

ADTS1

ADTS0

ADCSRB

Read/Write

R/W

Initial Value

Table 25-7. ADC Auto Trigger Source Selections

ADTS2

ADTS1

ADTS0

Trigger Source

Free Running mode

Analog Comparator

External Interrupt Request 0

Timer/Counter0 Compare Match A

Timer/Counter0 Overflow

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